1. Field of the Invention
The present invention relates to a solid-state imaging apparatus.
2. Description of the Related Art
In recent years, MOS-type solid-state imaging apparatuses have been widespread for use in digital cameras and scanners. This is partly because this type of apparatus has been capable of providing high S/N ratios. It is useful for providing an amplifier for each read out circuit for each column of a pixel matrix array for providing a high S/N ratio. Since the apparatuses provide gains by an amplifier at each column so as to suppress the gain to be given at a latter stage, amplifying a noise made at the latter stage is not needed. Consequently, the apparatuses can achieve higher S/N ratios.
In Japanese Patent Application Laid-Open No. 2003-228457 (hereinafter referred to as Patent Document 1), multiple columns are adapted to share an amplifying unit which is usually provided for each column so that the number of circuit elements is reduced, thereby the area of a chip is reduced.
As described in Patent Document 1, while a resetting operation is performed for the amplifying unit, the potential of the electrode at the amplifying unit side of each sampling capacitor is fixed to a reference potential via a sampling switch. The clamping operation for holding optical signals from two columns of pixels into first and second sampling capacitors in this state is performed by simultaneously performing Open/Close operations on the first and second sampling switches to write a reset signal for the pixel into each sampling capacitor. Hereinafter, turning the switch ON by the Open operation is referred to as the ON operation and turning the switch OFF by the Close operation is referred to as the OFF operation. The Open/Close operation is referred to as the ON/OFF operation.
After the reset of the amplifying unit is cancelled and the pixels are made into the reset state, pixel signals at the first column are read out from the amplifying unit by turning ON/OFF the first sampling switch. After resetting the amplifying unit again, pixel signals at the second column are read out by turning ON/OFF the second sampling switch. The ON/OFF operation is controlled by a driving pulse which is input into each sampling switch.
In Japanese Patent Application Laid-Open No. 2007-194720 (hereinafter referred to as Patent Document 2), a configuration is disclosed such that a pixel region in one row is divided into two of a first group and a second group so that vertical transferring to a memory unit for the first group and horizontal transferring for reading out from the memory unit for the second group are performed simultaneously and vertical transferring for the second group and horizontal transferring for the first group are performed simultaneously.
An inversion input terminal and an output terminal of a differential amplifier circuit which form common nodes are short circuited during the clamping operation. For example, when the differential amplifier circuit is a differential pair made of MOS transistors, the output terminal and a non-inversion input terminal to which a reference potential is connected are capacitively coupled to each other through a parasitic capacity between a gate and a drain of the MOS transistor. Since reference potential wiring is usually shared by all the differential amplifier circuits, as the number of columns increases, both the number of common nodes which capacitively coupled to the reference potential wiring and the number of sampling switches which perform the ON/OFF operation during the clamping operation increase. Therefore, the more the number of columns is, the more a change in the voltage of each common node changes the reference potential. Since the changed reference potential returns to the original potential according to a time constant which is determined by a driving force of the reference voltage source as well as the parasitic capacity and the parasitic resistance of the reference potential wiring, the changed reference potential changes as the above-mentioned common node does. Since the common node changes concomitantly to the change in the reference potential during the clamping operation, the above-mentioned change of the common node is amplified. That is, a large solid-state imaging apparatus with the more the number of columns generates the bigger fixed pattern noise (hereinafter referred to as FPN).
As scanning is performed separately on the two groups in the configuration disclosed by Patent Document 2, the above-mentioned problem may occur within the same group.
Here, the above-mentioned problem does not occur limitedly to the configuration in which the amplifying unit is connected to the sampling capacitor via a switch. FIG. 14A illustrates the above-mentioned circuit part exclusively. As illustrated in the figure, since the reset switch which is connected between the inversion input terminal and the output terminal of the differential amplifier circuit is in the conduction state during the clamping operation, both of the terminals are short circuited. Since the non-inversion input terminal and the inversion input terminal are substantially grounded, the differential amplifier circuit adjusts the voltage of the output terminal by itself to keep both of the terminals at the same potential. As illustrated in FIG. 14B, however, it can be easily understood that all of the above-mentioned changes in the potential may also occur to the configuration in which the reference voltage source is simply connected to the reset switch which is for supplying a reference level to the output node of the sampling capacitor.
The present invention is adapted in view of the above-mentioned problem and an object of the present invention is to provide a driving method with a reduced fixed pattern noise to a solid-state imaging apparatus which supplies a reference level to the output nodes of a predetermined number of signal holding units by a selecting unit for each group of the signal holding units.